High speed microprocessor systems currently require TTL level clock signals running at frequencies on the order of 100 MHz. For proper operation at such high frequencies, low skew between in phase clock signals at various locations within the system is essential. High speed system design typically allocates less than 5% to 10% of the clock cycle to accommodate skew. Maximum common edge skew between in phase clock signals must therefore be limited to less than approximately 500 pS. Low skew or minimum skew clock driver circuits are designed to meet these demanding specifications. However a dilemma arises in attempting to achieve accurate production testing of such minimum skew devices. The low skew specifications exceed the measurement capabilities of most if not all current automatic test equipment.
A standard definition of the output skew parameter tOSLH for an IC clock driver circuit having a primary clock signal input and n (at least 2) secondary clock signal outputs is illustrated in FIG. 1. According to this definition, a single clock input signal provides a time zero reference t.sub.0 for measuring propagation time tplh from the clock input signal at time t.sub.0 to a specified point in the low to high (LH) transition at the selected output. For example, at TTL voltage levels the input switching threshold is typically at 1.5 v and propagation time and skew are measured at the 1.5 v voltage level. Propagation time and skew may be measured at other threshold points of the LH transition for other IC device families.
Because of circuit layout and package lead frame parasitic differences, a range of different propagation times tplh for the secondary clock signals at the n multiple outputs can be expected. The output skew parameter tOSLH is the maximum difference in propagation times tplh between the fastest and slowest outputs of the multiple output circuit. Referring to FIG. 1, if the propagation time for the output signal on output 1 is the smallest propagation time tplhmin, and the propagation time for the output signal on output 2 is the greatest propagation time tplhmax, then the maximum output skew parameter tOSLH for the device is defined as: EQU tOSLH=tplhmax-tplhmin.
Similarly the output skew parameter tOSHL for common edge high to low transitions HL is defined as: EQU tOSHL=tphlmax-tphlmin.
It is noted that the output skew parameters tOSLH and tOSHL represent the maximum timing skew or timing difference between the multiple common edge outputs themselves without any necessary reference to the time t.sub.0 of the corresponding input signal edge.
An example of a conventional tester used for measuring output skew parameters tOSLH and tOSHL is the MCT tester, a microprocessor controlled digital IC device tester described for example in the MCT 2000R TEST SYSTEMS HARDWARE MANUAL, Publication No. 010193B, Revision B, Nov. 1, 1986, C 1986 MCT, Microcomponent Technology, Inc., 38 North Victoria Street, P.O. Box 64013, St. Paul, Minn. 55164 and also described in U.S. Pat. No. 5,101,153. A problem with such conventional testers is the limited bandwidth and limited resolution available for testing. As the speed of IC parts and devices has increased, equalling and exceeding the speed of the tester, large errors in testing measurement occur. For example, the tester pin electronics and precision measurement unit (PMU) have a certain limited rise time. As the rise time of the DUT part approaches the rise time of the tester, the result is increasing error in the rise time of output signals displayed on the screen. Skew testing for high speed low skew parts generally eludes such conventional testers.
Further discussion of testing output timing skew between multiple output signals is found in the Harry Vlahos U.S. patent application Ser. No. 769,940 filed Sep. 30, 1991 for DIRECT DIGITAL SYNTHESIS MEASUREMENT SIGNAL SKEW TESTER, now U.S. Pat. No. 5,231,598, issued Jul. 27, 1993.
To overcome the limitations of such a conventional tester, special "test heads" are required. Compensating software algorithms are encoded into the test program to estimate actual output skew. Alternatively, expensive new testers have been developed with higher resolution in an endeavor to match the speed of the DUT. For high speed minimum skew parts, output skew is also sometimes "guaranteed by design". That is, output skew is not tested in final production but is calculated and specified from data measured during the thorough device characterization and testing performed by the manufacturer. This approach may be necessitated by the hardware limitations of existing testers.
Another disadvantage of conventional testers is that output skew across all n outputs of a multiple output circuit cannot be measured directly and simultaneously. Rather, signal propagation times tplh and tphl are measured with reference to an input signal. Output skew is therefore a derivative parameter subject to the variables in measurement of separate propagation times through the part from input to multiple outputs. Or, the hardware limitations constrain comparative measurements at the output to skew measurements between two outputs at a time. In order to provide a complete test of output skew across n outputs, a series summation of separate measurements must be performed. For testing skew across 8 bits, for example 28 separate tests must be performed. For testing skew across 16 bits, 120 tests are required etc.